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1 of 25 rev: 072806 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . general description the ds5002fp secure microprocessor chip is a secure version of the ds5001fp 128k soft microprocessor chip. in addition to the memory and i/o enhancements of the ds5001fp, the secure microprocessor chip incorporates the most sophisticated security features available in any processor. the security features of the ds5002fp include an array of mechanisms that are designed to resist all levels of thre at, including observation, analysis, and physical attack. as a result, a massive effort is required to obtain any information about memory contents. furthermo re, the ?soft? nature of the ds5002fp allows frequent modification of the secure information, thereby minimizing the value of any secure information obtained by such a massive effort. pin configuration features 8051-compatible microprocessor for secure/sensitive applications access 32kb, 64kb, or 128kb of nv sram for program and/or data storage in-system programming through on-chip serial port can modify its own program or data memory in the end system firmware security features memory stored in encrypted form encryption using on-chip 64-bit key automatic true random key generator self destruct input (sdi) optional top coating prevents microprobe (ds5002fpm) improved security over previous generations protects memory contents from piracy crash-proof operation maintains all nonvolatile resources for over 10 years in the absence of power power-fail reset early warning power-fail interrupt watchdog timer ordering information part temp range internal micro probe shield pin- package ds5002fpm-16 0c to +70c yes 80 qfp ds5002fpm-16+ 0c to +70c yes 80 qfp DS5002FMN-16 -40c to +85c yes 80 qfp DS5002FMN-16+ -40c to +85c yes 80 qfp + denotes a pb-free/rohs-compliant device. selector guide appears at end of data sheet. ds5002fp secure microprocessor chip www.maxim-ic.com p0.4ad4 c e 2 p e 2 ba9 p0.3/ad3 ba8 p0.2/ad2 ba13 p0.1/ad1 r/ w p0.0/ad0 v cc0 v cc msel p1.0 ba14 p1.1 ba12 p1.2 ba7 p1.3 p e 3 p e 4 ba6 p2.6/a14 c e 3 c e 4 bd3 p2.5/a13 bd2 p2.4/a12 bd1 p2.3/a11 bd0 vli sdi gnd p2.2/a10 p2.1/a9 p2.0/a8 xtal1 xtal2 p3.7/ rd p3.6/ wr p3.5/ti pf v rst p3.4/t0 dallas semiconductor ds5002fp 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p1.4 ba5 p1.5 ba4 p1.6 ba3 p1.7 pro g ba2 rst ba1 p3.0/rxd ba0 p3.1/txd p3.2/int0 p3.3/int1 ba11 p0.5/ad5 p e 1 p0.6/ad6 ba10 p0.7/ad7 c e 1 n.c. c e1n bd7 ale bd6 n.c. bd5 p2.7/a15 bd4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 qfp top view
ds5002fp secure microprocessor chip 2 of 25 electrical spec ifications the ds5002fp adheres to all ac and dc electrical specifications published for the ds5001fp. absolute maximum ratings voltage range on any pin relative to ground?????????????????????.-0.3v to (v cc + 0.5v) voltage range on v cc relative to ground??????????????????????????-0.3v to +6.0v operating temperature range??????????????????????????????..-40c to +85c storage temperature* ...????????????????????????????????..-55 c to +125c soldering temperature?????????????????????.....see ipc/jedec j-std-020 specification this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time can affect reliability. * storage temperature is defined as the temperature of the device when v cc = 0v and v li = 0v. in this state the contents of sram are not battery-backed and are undefined. dc characteristics (v cc = 5v 10%, t a = 0c to +70c.)** parameter symbol conditions min typ max units input low voltage v il (note 1) -0.3 +0.8 v input high voltage v ih1 (note 1) 2.0 v cc + 0.3 v input high voltage (rst, xtal1, prog ) v ih2 (note 1) 3.5 v cc + 0.3 v output low voltage at i ol = 1.6ma (ports 1, 2, 3, pf ) v ol1 (notes 1, 13) 0.15 0.45 v output low voltage at i ol = 3.2ma (ports 0, ale, ba15?0, bd7?0, r/ w , ce1n , ce 1?4, pe 1?4, v rst ) v ol2 (note 1) 0.15 0.45 v output high voltage at i oh = -80a (ports 1, 2, 3) v oh1 (note 1) 2.4 4.8 v output high voltage at i oh = -400a (ports 0, ale, ba15?0, bd7?0, r/ w , ce1n , ce 1?4, pe 1?4, v rst ) v oh2 (note 1) 2.4 4.8 v input low current v in = 0.45v (ports 1, 2, 3) i il -50 a 0c to +70c -500 transition current; 1 to 0 v in = 2.0v (ports 1, 2, 3) i tl -40c to +85c (note 12) -600 a sdi input low voltage v ils (note 1) 0.4 v sdi input high voltage v ihs (notes 1, 11) 2.0 v cco v sdi pulldown resistor r sdi 25 60 k ? input leakage (port 0, msel) i il 0.45 < v in < v cc +10 a 0c to +70c 40 150 rst pulldown resistor r re -40c to +85c (note 12) 30 180 k ? vrst pullup resistor r vr 4.7 k ? prog pullup resistor r pr 40 k ? 0c to +70c (note 1) 4.25 4.37 4.5 power-fail warning voltage v pfw -40c to +85c (notes 1, 12) 4.1 4.37 4.6 v 0c to +70c (note 1) 4.00 4.12 4.25 minimum operating voltage v ccmin -40c to +85c (notes 1, 12) 3.85 4.09 4.25 v operating voltage v cc (note 1) v ccmin 5.5 v
ds5002fp secure microprocessor chip 3 of 3 dc characteristics (continued) (v cc = 5v 10%, t a = 0c to +70c.)** parameter symbol conditions min typ max units lithium supply voltage v li (note 1) 2.5 4.0 v operating current at 16mhz i cc (note 2) 36 ma 0c to +70c (note 3) 7.0 idle mode current at 12mhz i idle -40c to +85c (notes 3, 12) 8.0 ma stop mode current i stop (note 4) 80 a pin capacitance c in (note 5) 10 pf output supply voltage (v cco ) v cco1 (notes 1, 2) v cc -0.45 v 0c to +70c (notes 1, 8) v li -0.65 output supply battery-backed mode (v cco , ce 1?4, pe 1?2) v cco2 -40c to +85c (notes 1, 8, 12) v li -0.9 v output supply current (note 6) i cco1 v cco = v cc - 0.45v 75 ma 0c to +70c 5 75 lithium-backed quiescent current (note 7) i li -40c to +85c 75 500 na bat = 3.0v (0c to +70c) (note 1) 4.0 4.25 bat = 3.0v (-40c to +85c) (notes 1, 12) 3.85 4.25 reset trip point in stop mode bat = 3.3v (0c to +70c) (note 1) 4.4 4.65 ** all parameters apply to both commercial and industria l temperature operation unless otherwise noted. note 1: all voltages are referenced to ground. note 2: maximum operating i cc is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf = 10 ns, v il = 0.5v; xtal2 disconnected; rst = port0 = v cc , msel = v ss . note 3: idle mode i idle is measured with all output pins disconnected; xtal1 driven with t clkr ,t clkf = 10ns, v il = 0.5v; xtal2 disconnected; port0 = v cc , rst = msel = v ss . note4: stop mode i stop is measured with all output pins disconnected; port0 = v cc ; xtal2 not connected; rst = msel = xtal1 = v ss . note 5: pin capacitance is measured wi th a test frequency: 1mhz, t a = +25c. note 6: i cco1 is the maximum average operating current that can be drawn from v cco in normal operation. note 7: i li is the current drawn from v li input when v cc = 0v and v cco is disconnected. battery-backed mode is 2.5v v bat 4.0; v cc v bat ; v sdi should be v ils for i bat max. note 8: v cco2 is measured with v cc < v li , and a maximum load of 10a on v cco . note 9: crystal startup time is the time required to get the mass of the crystal into vibrational motion from the time that power is fi rst applied to the circuit until the first clock pulse is produced by the on-chip oscillator. the user should check with the crysta l vendor for a worst-case s pecification on this time. note 10: sdi is deglitched to prevent accidental des truction. the pulse must be longer than t spr to pass the deglitcher, but sdi is not guaranteed unless it is longer than t spa . note 11: v ihs minimum is 2.0v or v cco , whichever is lower. note 12: this parameter applies to i ndustrial temperature operation. note 13: pf pin operation is specified with v bat 3.0v. ac characteristics?sdi pin (v cc = 0v to 5v, t a = 0c to +70c.) parameter symbol conditions min typ max units 4.5v < v cc < 5.5v 1.3 sdi pulse reject (note 10) t spr v cc = 0v, v bat = 2.9v 4 s 4.5v < v cc < 5.5v 10 sdi pulse accept (note 10) t spa v cc = 0v, v bat = 2.9v 50 s
ds5002fp secure microprocessor chip 4 of 25 ac characteristics?expanded bus mode timing specifications (v cc = 5v 10%, t a = 0c to +70c.) ( figure 1 and figure 2 ) # parameter symbol conditions min max units 1 oscillator frequency 1 / t clk 1.0 16 mhz 2 ale pulse width t alpw 2t clk - 40 ns 3 address valid to ale low t avall t clk - 40 ns 4 address hold after ale low t avaav t clk - 35 ns 14 rd pulse width t rdpw 6t clk - 100 ns 15 wr pulse width t wrpw 6t clk - 100 ns 12mhz 5t clk - 165 16 rd low to valid data in t rdldv 16mhz 5t clk - 105 ns 17 data hold after rd high t rdhdv 0 ns 18 data float after rd high t rdhdz 2t clk - 70 ns 12mhz 8t clk - 150 19 ale low to valid data in t allvd 16mhz 8t clk - 90 ns 12mhz 9t clk - 165 20 valid address to valid data in t avdv 16mhz 9t clk - 105 ns 21 ale low to rd or wr low t allrdl 3t clk - 50 3t clk + 50 ns 22 address valid to rd or wr low t avrdl 4t clk - 130 ns 23 data valid to wr going low t dvwrl t clk - 60 ns 12mhz 7t clk - 150 24 data valid to wr high t dvwrh 16mhz 7t clk - 90 ns 25 data valid after wr high t wrhdv t clk -50 ns 26 rd low to address float t rdlaz 0 ns 27 rd or wr high to ale high t rdhalh t clk - 40 t clk + 50 ns figure 1. expanded data memory read cycle
ds5002fp secure microprocessor chip 5 of 25 figure 2. expanded data memory write cycle ac characteristics?external clock drive (v cc = 5v 10%, t a = 0c to +70c.) ( figure 3 ) # parameter symbol conditions min max units 12mhz 20 28 external clock high time t clkhpw 16mhz 15 ns 12mhz 20 29 external clock low time t clklpw 16mhz 15 ns 12mhz 20 30 external clock rise time t clkr 16mhz 15 ns 12mhz 20 31 external clock fall time t clkf 16mhz 15 ns figure 3. external clock timing
ds5002fp secure microprocessor chip 6 of 25 ac characteristics?power cycle time (v cc = 5v 10%, t a = 0c to +70c.) ( figure 4 ) # parameter symbol min max units 32 slew rate from v ccmin to v li t f 130 s 33 crystal startup time t csu (note 9) 34 power-on reset delay t por 21504 t clk figure 4. power cycle timing
ds5002fp secure microprocessor chip 7 of 25 ac characteristics?serial port timing, mode 0 (v cc = 5v 10%, t a = 0c to +70c.) ( figure 5 ) # parameter symbol min max units 35 serial port clock cycle time t spclk 12t clk s 36 output data setup to rising clock edge t doch 10t clk - 133 ns 37 output data hold after rising clock edge t chdo 2t clk - 117 ns 38 clock rising edge to input data valid t chdv 10t clk - 133 ns 39 input data hold after rising clock edge t chdiv 0 ns figure 5. serial port timing, mode 0
ds5002fp secure microprocessor chip 8 of 25 ac characteristics?byte-wide address/data bus timing (v cc = 5v 10%, t a = 0c to +70c.) ( figure 6 ) # parameter symbol min max units 40 delay to byte-wide address valid from ce1 , ce2 , or ce1n low during op code fetch t ce1lpa 30 ns 41 pulse width of ce 1?4, pe 1?4, or ce1n t cepw 4t clk - 35 ns 42 byte-wide address hold after ce1 , ce2 , or ce1n high during op code fetch t ce1hpa 2t clk - 20 ns 43 byte-wide data setup to ce1 , ce2 , or ce1n high during op code fetch t ovce1h 1t clk + 40 ns 44 byte-wide data hold after ce1 , ce2 , or ce1n high during op code fetch t ce1hov 0 ns 45 byte-wide address hold after ce 1?4, pe 1?4, or ce1n high during movx t cehda 4t clk - 30 ns 46 delay from byte-wide address valid ce 1?4, pe 1?4, or ce1n low during movx t celda 4t clk - 35 ns 47 byte-wide data setup to ce 1?4, pe 1?4, or ce1n high during movx (read) t daceh 1t clk + 40 ns 48 byte-wide data hold after ce 1?4, pe 1?4, or ce1n high during movx (read) t cehdv 0 ns 49 byte-wide address valid to r/ w active during movx (write) t avrwl 3t clk - 35 ns 50 delay from r/ w low to valid data out during movx (write) t rwldv 20 ns 51 valid data out hold time from ce 1?4, pe 1?4, or ce1n high t cehdv 1t clk - 15 ns 52 valid data out hold time from r/ w high t rwhdv 0 ns 53 write pulse width (r/ w low time) t rwlpw 6t clk - 20 ns figure 6. byte-wide bus timing
ds5002fp secure microprocessor chip 9 of 25 rpc ac characteristics, dbb read (v cc = 5v 10%, t a = 0c to +70c.) ( figure 7 ) # parameter symbol min max units 54 cs , a 0 setup to rd t ar 0 ns 55 cs , a 0 hold after rd t ra 0 ns 56 rd pulse width t rr 160 ns 57 cs , a 0 to data out delay t ad 130 ns 58 rd to data out delay t rd 0 130 ns 59 rd to data float delay t rdz 85 ns rpc ac characteristics, dbb write (v cc = 5v 10%, t a = 0c to +70c.) ( figure 7 ) # parameter symbol min max units 60 cs , a 0 setup to wr t aw 0 ns 61a cs , hold after wr t wa 0 ns 61b a 0 , hold after wr t wa 20 ns 62 wr pulse width t ww 160 ns 63 data setup to wr t dw 130 ns 64 data hold after wr t wd 20 ns ac characteristics, dma (v cc = 5v 10%, t a = 0c to +70c.) # parameter symbol min max units 65 dack to wr or rd t acc 0 ns 66 rd or wr to dack t cac 0 ns 67 dack to data valid t acd 0 130 ns 68 rd or wr to drq cleared t crq 110 ns ac characteristics, prog (v cc = 5v 10%, t a = 0c to +70c.) # parameter symbol min max units 69 prog low to active t pra 48 clks 70 prog high to inactive t pri 48 clks
ds5002fp secure microprocessor chip 10 of 25 figure 7. rpc timing mode
ds5002fp secure microprocessor chip 11 of 25 pin description pin name function 11, 9, 7, 5, 1, 79, 77, 75 p0.0?p0.7 general-purpose i/o port 0. this port is open-drain and cannot drive a logic 1. it requires external pullups. port 0 is also the multiplexed expanded address/data bus. when used in this mode, it does not require pullups. 15, 17, 19, 21, 25, 27, 29, 31 p1.0?p1.7 general-purpose i/o port 1 49, 50, 51, 56, 58, 60, 64, 66 p2.0?p2.7 general-purpose i/o port 2. also serves as the msb of the expanded address bus. 36 p3.0/rxd general-purpose i/o port pin 3.0. also serves as the receive signal for the on-board uart. this pin should not be connected directly to a pc com port. 38 p3.1/txd general-purpose i/o port pin 3.1. also serves as the transmit signal for the on-board uart. this pin should not be connected directly to a pc com port. 39 p3.2/ int0 general-purpose i/o port pin 3.2. also serves as the active-low external interrupt 0. 40 p3.3/ int1 general-purpose i/o port pin 3.3. also serves as the active-low external interrupt 1. 41 p3.4/t0 general-purpose i/o port pin 3.4. also serves as the timer 0 input. 44 p3.5/t1 general-purpose i/o port pin 3.5. also serves as the timer 1 input. 45 p3.6/ wr general-purpose i/o port pin. also serves as the write strobe for expanded bus operation. 46 p3.7/ rd general-purpose i/o port pin. also serves as the read strobe for expanded bus operation. 34 rst active-high reset input. a logic 1 applied to this pin activates a reset state. this pin is pulled down internally so this pin can be left unconnected if not used. an rc power-on reset circuit is not needed and is not recommended. 70 ale address latch enable. used to demultiplex the multiplexed expanded address/data bus on port 0. this pin is normally connected to the clock input on a ?373 type transparent latch. 47, 48 xtal2, xtal1 crystal connections. used to connect an external crystal to the internal oscillator. xtal1 is the input to an inverting amplifier and xtal2 is the output. 52 gnd logic ground 13 v cc power supply, +5v 12 v cco v cc output. this is switched between v cc and v li by internal circuits based on the level of v cc . when power is above the lithium input, power is drawn from v cc . the lithium cell remains isolated from a load. when v cc is below v li , the v cco switches to the v li source. v cco should be connected to the v cc pin of an sram. 54 v li lithium voltage input. connect to a lithium cell greater than v limin and no greater than v limax as shown in the electrical specifications. nominal value is +3v. 16, 8, 18, 80, 76, 4, 6, 20, 24, 26, 28, 30, 33, 35, 37 ba14?ba0 byte-wide address bus bits 14?0. this bus is combined with the nonmultiplexed data bus (bd7?bd0) to access nv sram. decoding is performed using ce1 to ce4 . therefore, ba15 is not actually needed. read/write access is controlled by r/ w . ba14?0 connect directly to an 8k, 32k, or 128k sram. if an 8k ram is used, ba13 and ba14 are unconnected. if a 128k sram is used, the micro converts ce2 and ce3 to serve as a16 and a15, respectively. 71, 69, 67, 65, 61, 59, 57, 55 bd7?bd0 byte-wide data bus bits 7?0. this 8-bit bidirectional bus is combined with the nonmultiplexed address bus (ba14?ba0) to access nv sram. decoding is performed on ce1 and ce2 . read/write access is controlled by r/ w. d7?d0 connect directly to an sram, and optionally to a real-time clock or other peripheral. 10 r/ w read/write (active low). this signal provides the write enable to the srams on the byte- wide bus. it is controlled by the memory map and partition. the blocks selected as program (rom) are write-protected. 74 ce1 active-low chip enable 1. this is the primary decoded chip enable for memory access on the byte-wide bus. it connects to the chip-enable input of one sram. ce1 is lithium-backed. it remains in a logic-high inactive state when v cc falls below v li . 2 ce2 active-low chip enable 2. this chip enable is provided to access a second 32k block of memory. it connects to the chip-enable input of one sram. when msel = 0, the micro converts ce2 into a16 for a 128k x 8 sram. ce2 is lithium-backed and remains at a logic high when v cc falls below v li . 63 ce3 active-low chip enable 3. this chip enable is provided to access a third 32k block of memory. it connects to the chip enable input of one sram. when msel = 0, the micro converts ce3 into a15 for a 128k x 8 sram. ce3 is lithium-backed and remains at a logic high when v cc falls below v li .
ds5002fp secure microprocessor chip 12 of 25 pin name function 62 ce4 active-low chip enable 4. this chip enable is provided to access a fourth 32k block of memory. it connects to the chip-enable input of one sram. when msel = 0, this signal is unused. ce4 is lithium-backed and remains at a logic high when v cc falls below v li . 78 pe1 active-low peripheral enable 1. accesses data memory between addresses 0000h and 3fffh when the pes bit is set to a logic 1. commonly used to chip enable a byte-wide real- time clock such as the ds1283. pe1 is lithium-backed and will remain at a logic high when v cc falls below v li . connect pe1 to battery-backed functions only. 3 pe2 active-low peripheral enable 2. accesses data memory between addresses 4000h and 7fffh when the pes bit is set to a logic 1. pe2 is lithium-backed and will remain at a logic high when v cc falls below v li . connect pe2 to battery-backed functions only. 22 pe3 active-low peripheral enable 3. accesses data memory between addresses 8000h and bfffh when the pes bit is set to a logic 1. pe3 is not lithium-backed and can be connected to any type of peripheral function. if connected to a battery-backed chip, it will need additional circuitry to maintain the chip enable in an inactive state when v cc < v li . 23 pe4 active-low peripheral enable 4. accesses data memory between addresses c000h and ffffh when the pes bit is set to a logic 1. pe4 is not lithium-backed and can be connected to any type of peripheral function. if connected to a battery-backed chip, it will need additional circuitry to maintain the chip enable in an inactive state when v cc < v li . 32 prog invokes the bootstrap loader on falling edge. this signal should be debounced so that only one edge is detected. if connected to ground, the micro enters bootstrap loading on power-up. this signal is pulled up internally. 42 vrst this i/o pin (open drain with internal pullup) indicates that the power supply (v cc ) has fallen below the v ccmin level and the micro is in a reset state. when this occurs, the ds5002fp drives this pin to a logic 0. because the micro is lithium-backed, this signal is guaranteed even when v cc = 0v. because it is an i/o pin, it also forces a reset if pulled low externally. this allows multiple parts to synchronize their power-down resets. 43 pf this output goes to a logic 0 to indicate that the micro has switched to lithium backup. this corresponds to v cc < v li . because the micro is lithium-backed, this signal is guaranteed even when v cc = 0v. the normal application of this signal is to control lithium-powered current to isolate battery-backed functions from non-battery-backed functions. 14 msel memory select. this signal controls the memory size selection. when msel = +5v, the ds5002fp expects to use 32k x 8 srams. when msel = 0v, the ds5002fp expects to use a 128k x 8 sram. msel must be connected regardless of partition, mode, etc. 53 sdi self-destruct input. an active high on this pin causes an unlock procedure. this results in the destruction of vector ram, encryption keys, and the loss of power from v cco . this pin should be grounded if not used. 72 ce1n non-battery-backed version of ce1 . it is not generally useful since the ds5002fp cannot be used with eprom due to its encryption. 73 n.c. no connection
ds5002fp secure microprocessor chip 13 of 25 detailed description the ds5002fp implements a security system that is an improved version of its predecessor, the ds5000fp. like the ds5000fp, the ds5002fp loads and executes application software in encrypted form. up to 128kb of standard sram can be accessed by its byte-wide bus. this ram is converted by the ds5002fp into lithium- backed nonvolatile storage for program and data. data is maintained for over 10 years at room temperature with a very small lithium cell. as a result, the contents of the ram and the execution of the software appear unintelligible to the outside observer. the encryption algorithm uses an internally stored and protected key. any attempt to discover the key value results in its erasure, rendering the encrypted contents of the ram useless. the secure microprocessor chip offers a number of major enhancements to the software security implemented in the previous generation ds5000fp. first, the ds5002fp provides a stronger software encryption algorithm that incorporates elements of des encryption. second, the encryption is based on a 64-bit key word, as compared to the ds5000fp?s 40-bit key. third, the key can only be loaded from an on-chip true random-number generator. as a result, the true key value is never known by the user. fourth, a self-destruct input (sdi) pin is provided to interface to external tamper-detection circuitry. with or without the presence of v cc , activation of the sdi pin has the same effect as resetting the security lock: immediate erasure of the key word and the 48-byte vector ram area. fifth, an optional top-coating of the die prevents access of information using microprobing techniques. finally, customer- specific versions of the ds5002fp are available that incorporate a one-of-a-kind encryption algorithm. when implemented as a part of a secure system design, a system based on the ds5002fp can typically provide a level of security that requires more time and resources to defeat than it is worth to unauthorized individuals who have reason to try. for a user who wants a preconstructed module using the ds5002fp, ram, lithium cell, and a real-time clock, the ds2252t is available and described in a separate data sheet. block diagram figure 8 is a block diagram illustrating the internal architecture of the ds5002fp. the ds5002fp is a secure implementation of the ds5001fp 128k soft microprocessor chip. as a result, it operates in an identical fashion to the ds5001fp, except where indicated. see the ds5001fp data sheet for operating details.
ds5002fp secure microprocessor chip 14 of 25 figure 8. block diagram
ds5002fp secure microprocessor chip 15 of 25 secure operation overview the ds5002fp incorporates encryption of the activity on its byte-wide address/data bus to prevent unauthorized access to the program and data information contained in the nv ram. loading an application program in this manner is performed by the bootstrap loader using the general sequence described below: 1) clear security lock. 2) set memory map configuration as for ds5001fp 3) load application software 4) set security lock 5) exit loader loading of application software into the program/data ram is performed while the ds5002fp is in its bootstrap load mode. loading is only possible when the security lock is clear. if the security lock has previously set, then it must be cleared by issuing the ?z? command from the bootstrap loader. resetting the security lock instantly clears the previous key word and the contents of the vector ram. in addition, the bootstrap rom writes 0?s into the first 32k of external ram. the user?s application software is loaded into external cmos sram by the ?l? command in ?scrambled? form through on-chip encryptor circuits. each external ram address is an encrypted representation of an on-chip logical address. thus, the sequential instructions of an ordinary program or data table are stored nonsequentially in ram memory. the contents of the program/data ram are also encrypted. each byte in ram is encrypted by a key- and address-dependent encryptor circuit such that identical bytes are stored as different values in different memory locations. the encryption of the program/data ram is dependent on an on-chip 64-bit key word. the key is loaded by the rom firmware just prior to the time that the application software is loaded, and is retained as nonvolatile information in the absence of v cc by the lithium backup circuits. after loading is complete, the key is protected by setting the on-chip security lock, which is also retained as nonvolatile information in the absence of v cc . any attempt to tamper with the key word and thereby gain access to the true program/data ram contents results in the erasure of the key word as well as the ram contents. during execution of the application software, logical addresses on the ds5002fp that are generated from the program counter or data pointer registers are encrypted before they are presented on the byte-wide address bus. op codes and data are read back and decrypted before they are operated on by the cpu. similarly, data values written to the external nonvolatile ram storage during program execution are encrypted before they are presented on the byte-wide data bus during the write operation. this encryption/decryption process is performed in real time such that no execution time is lost as compared to the non-encrypted ds5001fp or 8051 running at the same clock rate. as a result, operation of the encryptor circuitry is transparent to the application software. unlike the ds5000fp, the ds5002fp chip?s security feature is always enabled. security circuitry the on-chip functions associated with the ds5002fp?s software security feature are depicted in figure 9 . encryption logic consists of an address encryptor and a data encryptor. although each encryptor uses its own algorithm for encrypting data, both depend on the 64-bit key word which is contained in the encryption key registers. both the encryptors operate during loading of the application software and also during its execution.
ds5002fp secure microprocessor chip 16 of 25 figure 9. security circuitry the address encryptor translates each ?logical? address, i.e., the normal sequence of addresses that are generated in the logical flow of program execution, into an encrypted address (or ?physical? address) at which the byte is actually stored. each time a logical address is generated, either during program loading or during program execution, the address encryptor circuitry uses the value of the 64-bit key word and of the address itself to form the physical address, which are presented on the address lines of the ram. the encryption algorithm is such that there is one and only one physical address for every possible logical address. the address encryptor operates over the entire memory range, which is configured during bootstrap loading for access on the byte-wide bus. as bootstrap loading of the application software is performed, the data encryptor logic transforms the op code, operand, or data byte at any given memory location into an encrypted representation. as each byte is read back to the cpu during program execution, the internal data encryptor restores it to its original value. when a byte is written to the external nonvolatile program/ data ram during program execution, that byte is stored in encrypted form as well. the data encryption logic uses the value of the 64-bit key, the logical address to which the data is being written, and the value of the data itself to form the encrypted data, which is written to the nonvolatile program/data ram. the encryption algorithm is repeatable, such that for a given data value, encryption key value, and logical address the encrypted byte will always be the same. however, there are many possible encrypted data values for each possible true data value due to the algorithm?s dependency on the values of the logical address and encryption key. when the application software is executed, the internal cpu of the ds5002fp operates as normal. logical addresses are calculated for op code fetch cycles and also data read and write operations. the ds5002fp has the ability to perform address encryption on logical addresses as they are generated internally during the normal course of program execution. in a similar fashion, data is manipulated by the cpu in its true representation. however, it is also encrypted when it is written to the external program/data ram, and is restored to its original value when it is read back. when an application program is stored in the format described above, it is virtually impossible to disassemble op codes or to convert data back into its true representation. address encryption has the effect that the op codes and data are not stored in the contiguous form in which they were assembled, but rather in seemingly random locations in memory. this in itself makes it virtually impossible to determine the normal flow of the program. as an added
ds5002fp secure microprocessor chip 17 of 25 protection measure, the address encryptor also generates ?dummy? read access cycles whenever time is available during program execution. dummy read cycles like the ds5000fp, the ds5002fp generates a ?dummy? read access cycle to non-sequential addresses in external ram memory whenever time is available during program execution. this action has the affect of further complicating the task of determining the normal flow of program execution. during these pseudorandom dummy cycles, the ram is read to all appearances, but the data is not used internally. through the use of a repeatable exchange of dummy and true read cycles, it is impossible to distinguish a dummy cycle from a real one. encryption algorithm the ds5002fp incorporates a proprietary algorithm implemented in hardware, which performs the scrambling of address and data on the byte-wide bus to the sram. this algorithm has been greatly strengthened with respect to its ds5000fp predecessor. improvements include: 1) 64-bit encryption key 2) incorporation of des-like operations to provide a greater degree of nonlinearity 3) customizable encryption the encryption circuitry uses a 64-bit key value (compared to the ds5000fp?s 40-bit key), which is stored on the ds5002fp die and protected by the security lock function described below. in addition, the algorithm has been strengthened to incorporate certain operations used in des encryption, so that the encryption of both the addresses and data is highly nonlinear. unlike the ds5000fp, the encryption circuitry in the ds5002fp is always enabled. dallas semiconductor can customize the encryption circuitry by laser programming the die to insure that a unique encryption algorithm is delivered to the customer. in addition, the customer-specific version can be branded as specified by the customer. please contact dallas semiconductor for ordering information of customer-specific versions. encryption key as described above, the on-chip 64-bit encryption key is the basis of both the address and data encryptor circuits. the ds5002fp provides a key management system, which is greatly improved over the ds5000fp. the ds5002fp does not give the user the ability to select a key. instead, when the loader is given certain commands, the key is set based on the value read from an on-chip hardware random number generator. this action is performed just prior to actually loading the code into the external ram. this scheme prevents characterization of the encryption algorithm by continuously loading new, known keys. it also frees the user from the burden of protecting the key selection process. the random number generator circuit uses the asynchronous frequency differences of two internal ring oscillator and the processor master clock (determined by xtal1 and xtal2). as a result, a true random number is produced. vector ram a 48-byte vector ram area is incorporated on-chip, and is used to contain the reset and interrupt vector code in the ds5002fp. it is included in the architecture to help insure the security of the application program. if reset and interrupt vector locations were accessed from the external nonvolatile program/data ram during the execution of the program, then it would be possible to determine the encrypted value of known addresses. this could be done by forcing an interrupt or reset condition and observing the resulting addresses on the byte-wide address/data bus. for example, it is known that when a hardware reset is applied the logical program address is forced to location 0000h and code is executed starting from this location. it would then be possible to determine the encrypted value (or physical address) of the logical address value 0000h by observing the address presented to the external ram following a hardware reset. interrupt vector address relationships could be determined in a similar fashion. by using the on-chip vector ram to contain the interrupt and reset vectors, it is impossible to
ds5002fp secure microprocessor chip 18 of 25 observe such relationships. although it is very unlikely that an application program could be deciphered by observing vector address relationships, the vector ram eliminates this possibility. note that the dummy accesses mentioned above are conducted while fetching from vector ram. the vector ram is automatically loaded with the user?s reset and interrupt vectors during bootstrap loading. security lock once the application program has been loaded into the ds5002fp?s nv ram, the security lock can be enabled by issuing the ?z? command in the bootstrap loader. while the security lock is set, no further access to program/data information is possible by the on-chip rom. access is prevented by both the bootstrap loader firmware and the ds5002fp encryptor circuits. access to the nv ram can only be regained by clearing the security lock by the ?u? command in the bootstrap loader. this action triggers several events, which defeat tampering. first, the encryption key is instantaneously erased. without the encryption key, the ds5002fp is no longer able to decrypt the contents of the ram. therefore, the application software can no longer be correctly executed, nor can it be read back in its true form by the bootstrap loader. second, the vector ram area is also instantaneously erased, so that the reset and vector information is lost. third, the bootstrap loader firmware sequentially erases the encrypted ram area. lastly, the loader creates and loads a new random key. the security lock bit itself is constructed using a multiple-bit latch which is interlaced for self-destruct in the event of tampering. the lock is designed to set-up a ?domino-effect? such that erasure of the bit will result in an unstoppable sequence of events that clears critical data including encryption key and vector ram. in addition, this bit is protected from probing by the top-coating feature mentioned below. self-destruct input the self-destruct input (sdi) pin is an active-high input that is used to reset the security lock in response to an external event. the sdi input is intended to be used with external tamper-detection circuitry. it can be activated with or without operating power applied to the v cc pin. activation of the sdi pin instantly resets the security lock and causes the same sequence of events described above for this action. in addition, power is momentarily removed from the byte-wide bus interface including the v cco pin, resulting in the loss of data in external ram. top layer coating the ds5002fpm is provided with a special top-layer coating that is designed to prevent a probe attack. this coating is implemented with second-layer metal added through special processing of the microcontroller die. this additional layer is not a simple sheet of metal, but rather a complex layout that is interwoven with power and ground, which are in turn connected to logic for the encryption key and the security lock. as a result, any attempt to remove the layer or probe through it results in the erasure of the security lock and/or the loss of encryption key bits. bootstrap loading initial loading of application software into the ds5002fp is performed by firmware within the on-chip bootstrap loader communicating with a pc by the on-chip serial port in a manner that is almost identical to that for the ds5001fp. the user should consult the ds5001fp data sheet as a basis of operational characteristics of this firmware. certain differences in loading procedure exist in order to support the security feature. these differences are documented below. table 1 summarizes the commands accepted by the bootstrap loader. when the bootstrap loader is invoked, portions of the 128-byte scratchpad ram area are automatically overwritten with 0?s, and then used for variable storage for the bootstrap firmware. also, a set of 8 bytes are generated using the random number generator circuitry and are saved as a potential word for the 64-bit encryption key. any read or write operation to the ds5002fp?s external program/data sram can only take place if the security lock bit is in a cleared state. therefore, the first step in loading a program should be the clearing of the security lock bit through the ?u? command.
ds5002fp secure microprocessor chip 19 of 25 table 1. serial bootstrap loader commands command function c return crc-16 of the program/data nv ram d dump intel hex file f fill program/data nv ram g get data from p1, p2, and p3 i n/a on the ds5002fp l load intel hex file m toggle modem available bit n set freshness seal?all program and data is lost p put data into p0, p1, p2, and p3 r read status of nv sfrs (mcon, rpctl, msl, calib) t trace (echo) incoming intel hex code u clear security lock v verify program/data nv ram with incoming intel hex data w write special function registers (mcon, rpctl, msl, calib) z set security lock execution of certain bootstrap loader commands result in the loading of the newly generated 64-bit random number into the encryption key word. these commands are as follows: fill f load l dump d verify v crc c execution of the fill and load commands result in the data loaded into the nv ram in an encrypted form determined by the value of the newly generated key word. the subsequent execution of the dump command within the same bootstrap session causes the contents of the encrypted ram to be read out and transmitted back to the host pc in decrypted form. similarly, execution of the verify command within the same bootstrap session causes the incoming absolute hex data to be compared against the true contents of the encrypted ram, and the crc command returns the crc value calculated from the true contents of the encrypted ram. as long as any of the above commands are executed within the same bootstrap session , the loaded key value remains the same, and the contents of the encrypted program/data nv ram can be read or written normally and freely until the security lock bit is set. when the security lock bit is set using the z command, no further access to the true ram contents is possible using any bootstrap command or by any other means. instruction set the ds5002fp executes an instruction set that is object code-compatible with the industry standard 8051 microcontroller. as a result, software development packages such as assemblers and compilers that have been written for the 8051 are compatible with the ds5002fp. a complete description of the instruction set and operation are provided in the secure microcontroller user?s guide . also note that the ds5002fp is embodied in the ds2252t module. the ds2252t combines the ds5002fp with between 32k and 128k of sram, a lithium cell, and a real-time clock. this is packaged in a 40-pin simm module. memory organization figure 10 illustrates the memory map accessed by the ds5002fp. the entire 64k of program and 64k of data are potentially available to the byte-wide bus. this preserves the i/o ports for application use. the user controls the portion of memory that is actually mapped to the byte-wide bus by selecting the program range and data range. any area not mapped into the nv ram is reached by the expanded bus on ports 0 and 2. an alternate configuration allows dynamic partitioning of a 64k space as shown in figure 11 . selecting pes = 1 provides another 64k of potential data storage or memory mapped peripheral space as shown in figure 12 . these
ds5002fp secure microprocessor chip 20 of 25 selections are made using special function registers. the memory map and its controls are covered in detail in the secure microcontroller user?s guide . figure 10. memory map in nonpa rtitionable mode (pm = 1)
ds5002fp secure microprocessor chip 21 of 25 figure 11. memory map in partitionable mode (pm = 0) figure 12. memory map with pes = 1
ds5002fp secure microprocessor chip 22 of 25 figure 13 illustrates a typical memory connection for a system using a 128kb sram. note that in this configuration, both program and data are stored in a common ram chip. figure 14 shows a similar system with using two 32kb srams. the byte-wide address bus connects to the sram address lines. the bidirectional byte-wide data bus connects the data i/o lines of the sram. figure 13. connection to 128k x 8 sram
ds5002fp secure microprocessor chip 23 of 25 figure 14. connection to 64k x 8 sram power management the ds5002fp monitors v cc to provide power-fail reset, early warning power-fail interrupt, and switchover to lithium backup. it uses an internal bandgap reference in determining the switch points. these are called v pfw , v ccmin , and v li respectively. when v cc drops below v pfw , the ds5002fp will perform an interrupt vector to location 2bh if the power-fail warning was enabled. full processor operation continues regardless. when power falls further to v ccmin , the ds5002fp invokes a reset state. no further code execution is performed unless power rises back above v ccmin . all decoded chip enables and the r/ w signal go to an inactive (logic 1) state. v cc is still the power source at this time. when v cc drops further to below v li , internal circuitry switch to the lithium cell for power. the majority of internal circuits will be disabled and the remaining nonvolatile states will be retained. any devices connected v cco will be powered by the lithium cell at this time. v cco is at the lithium battery voltage minus approximately 0.45v (less a diode drop). this drop varies depending on the load. low-power srams should be used for this reason. when using the ds5002fp, the user must select the appropriate battery to match the ram data retention current and the desired backup lifetime. note that the lithium cell is only loaded when v cc < v li . the secure microcontroller user?s guide has more information on this topic. the trip points v ccmin and v pfw are listed in the electrical specifications.
ds5002fp secure microprocessor chip 24 of 25 selector guide standard part pb-free/rohs compliant temp range max clock speed (mhz) internal microprobe shield pin-package ds5002fp-16 ds5002fp-16+ 0c to +70c 16 no 80 qfp ds5002fpm-16 ds5002fpm-16+ 0c to +70c 16 yes 80 qfp ds5002fp-16n ds5002fp-16n+ -40c to +85c 16 no 80 qfp DS5002FMN-16 DS5002FMN-16+ -40c to +85c 16 yes 80 qfp package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/dallaspackinfo .) mm dim min max a ? 3.40 a1 0.25 ? a2 2.55 2.87 b 0.30 0.50 c 0.13 0.23 d 23.70 24.10 d1 19.90 20.10 e 17.70 18.10 e1 13.90 14.10 e 0.80 bsc l 0.65 0.95 56-g4005-001
ds5002fp secure microprocessor chip 25 of 25 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products the maxim logo is a registered trademark of maxim integrated produ cts, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. revision history revision description 112795 original release. 073096 change v cc02 specification from v li - 0.5 to v li - 0.65 (pcn f62501). update mechanical specifications. 111996 change v cc01 from v cc - 0.3 to v cc - 0.35. 061297 pf signal moved from v ol2 test specification to v ol1 . pcn no. (d72502). ac characteristics for battery-backed sdi pulse specification added. 051499 reduced absolute maximum voltage to v cc + 0.5v. added note clarifying storage temperature spec ification is for nonbattery-backed state. deleted i bat specification (duplicate of i li specification). changed rre min (industrial temp range) from 40k ? to 30k ? . changed v pfw max (industrial temp range) from 4.5v to 4.6v. added industrial specification for i li . reduced t ce1hov and t cehdv from 10ns to 0ns. 052599 minor revisions and approval. 062102 update v cco and i cco1 specifications to reflect 0.45v inte rnal voltage drop instead of 0.35v. 100102 ordering information updated. 030403 reset trip point in stop mode (dc characteristics) wi th bat = 3.0v was changed to 3.3v (original issue was 3.3v). 070605 added pb-free part numbers to ordering information and selector guide. added operating voltage spec ification. (this is not a new specification because o perating voltage is implied in the testing limits, but rather a clarification.) updated absolute maximum soldering temperature to reference jedec standard. 090805 in the ac characteristics?sdi pin table, changed t spr max (in active mode) from 2 s to 1.3 s. this change is only to correct a documentation error, and does not reflect a change in device operation or any change in testing. 072806 removed products from ordering information table th at do not contain internal micro probe shields.

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